Among solid-state imaging apparatuses, MOS (Metal Oxide Semiconductor) type imaging apparatuses include pixels two-dimensionally disposed on a substrate, each of which subjects input light to photoelectric conversion performed by a photodiode disposed in the pixel to generate signal charge, and amplifies the generated signal charge by an amplification circuit placed in the pixel. The amplified signal charge is to be read out from the pixel. Such MOS type imaging apparatuses can be driven with a low voltage and low power consumption. Also, an imaging region and a drive circuit region that drives the imaging region can be realized as one chip. In other words, they can be formed on one substrate. Therefore, the MOS type imaging apparatuses are attracting considerable attention as image input devices of portable appliances.
Conventional MOS type imaging apparatuses are structured in such a manner that the imaging region and the drive circuit region are formed on one silicon substrate (hereinafter called the “Si substrate”) based on CMOS (Complementary Metal Oxide Semiconductor) processing technology. In the CMOS processing technology, apparatuses and processes have been designed and developed with the main aim of making the driving speed faster.
The imaging region includes a plurality of pixels that are disposed on the Si substrate two-dimensionally (e.g. in a shape of a matrix). Each pixel includes a photodiode unit for converting received light to signal charge, a MOS type transistor for performing a switching function, and a MOS type transistor for amplifying signals.
The signal charge generated in the photodiode unit by the photoelectric conversion is amplified in each pixel by a switching operation based on instruction signals received from a vertical shift register and a horizontal shift register, which are included in a drive circuit region described later. Then the amplified signal is to be read out from each pixel.
Every MOS type transistor included in the imaging region is of an n-channel MOS type.
The drive circuit region includes four main circuits, namely a timing generator circuit, a vertical shift register, a horizontal shift register, and a pixel selection circuit. Every MOS type transistor included in the drive circuit region has a CMOS structure, which is a combination of an n-channel MOS type and a p-channel MOS type.
The n-channel MOS type transistors in the imaging region and then-channel MOS type transistors in the drive circuit region usually have the same structure.
The following describes the circuit structure of the horizontal shift register, with reference to FIG. 10. Generally, the horizontal shift register has several stages. The number of the stages is in accordance with the number of pixel lines. FIG. 10 shows only the 1st stage of the horizontal shift register.
As FIG. 10 shows, the 1st stage 50 of the horizontal shift register includes four switches 51, 54, 55 and 58, and four inverters 52, 53, 56 and 57. Each of the switches 51, 54, 55 and 58, and each of the inverters 52, 53, 56 and 57 includes a pair of an n-channel MOS type transistor and a p-channel MOS type transistor.
The inverters 52 and 53 are connected in series with each other. The pair of inverters 52 and 53 is connected in parallel with the switch 54. The switch 51 is connected in series with the group of the inverters 52 and 53 and the switch 54 that are in the above-described relation.
The switches 55 and 58 and the inverters 56 and 57 have the same relation as described above.
The 1st stage 50 of the horizontal shift register, having such a structure, starts the driving operation when being applied a start pulse VST by the switch 51, and outputs an operation pulse of the 1st stage to the pixel selection circuit when being applied a clock pulse CK1 and its inversion pulse CK2 twice for each. Then, the horizontal shift register outputs operation pulses of the 2nd and 3rd stages sequentially.
The following describes the device structure of a transistor (CMOS type) in the 1st stage of the horizontal shift register, with reference to FIG. 11. FIG. 11 is a cross-sectional view showing the device structure of the above-described switches 51, 54, 55 and 58, or inverters 52, 53, 56 and 57.
As FIG. 11 shows, an n-well 62 and a p-well 63 are formed underneath the surface of the Si substrate 61 with an interval.
A gate insulator 64 is formed on the surfaces of the Si substrate 61 so as to cover the n-well 62 and the p-well 63. Gate electrodes 67 and 70 are formed on the surface of the gate insulator 64 so as to be on a substantially center portions of the wells respectively.
Source regions 65 and 68, and drain regions 66 and 69 are formed underneath the boundary portion between the gate insulator 64 and the wells 62 and 63.
In such a manner, a p-channel MOS type transistor is formed on the Si substrate 61 from three electrodes, namely the gate electrode 67, the source region 65 and the drain region 66. Also, an n-channel MOS type transistor is formed on the Si substrate 61 from three electrodes, namely the gate electrode 70, the source region 68, and the drain region 69.
The MOS type imaging apparatus having the CMOS structure is formed through following steps 1 to 15 aimed at the Si substrate 61.    1. Form a resist for forming the n-well 62.    2. Form the n-well 62.    3. Remove the resist for forming the n-well 62.    4. Form a resist for forming the p-well 63.    5. Form the p-well 63.    6. Remove the resist for forming the p-well 63.    7. Form the gate insulator 64.    8. Form the gate electrodes 67 and 70.    9. Form a resist for forming the source region 65/the drain region 66 of n-channel MOS type.    10. Form the source region 65/the drain region 66 of n-channel MOS type.    11. Remove the resist for forming the source region 65/the drain region 66 of n-channel MOS type.    12. Form a resist for forming the source region 68/the drain region 69, which are of p-channel MOS type.    13. Form the source region 68/the drain region 69 of p-channel MOS type.    14. Remove the resist for forming the source region 68/the drain region 69 of p-channel MOS type.    15. Form the photodiode unit.
However, the conventional MOS type imaging apparatuses manufactured based on such a CMOS processing technology might suffer, in the imaging region, leakage current in the photodiode unit and characteristic deterioration in the amplification circuit during the driving operation, which become causes of a noise. When a noise is caused in the imaging region, it is amplified and output with the signal charge, resulting in deterioration of the image quality.